1. Field of Invention
This invention relates to logic gates (switching circuits) for high speed digital systems.
2. Prior Art
A class of logic circuit configurations of a non-inverting type known as Emitter Function Logic (EFL), providing performance of most of the logic operations at the emitter of a multi-emitter bipolar transistor, are described in the U.S. Pat. No. 3,795,822 to Z. E. Skokan dated Mar. 5, 1974 and entitled, "Multi-Emitter Coupled Logic Gate". These gates are also described in a paper entitled, "Emitter Function Logic-Family for LSI", by the inventor named in the foregoing patent and published in the IEEE Journal of Solid State Circuits, pages 356-361, October 1973.
The modification of the EFL type circuits to maintain the advantage of Current Mode Logic (CML) and to add to the family of logic functions by providing a complement output, not available in the EFL gate of Skokan, is described in the U.S. Pat. No. 4,145,623 entitled, "Current Mode Logic Compatible Emitter Function Type Logic Family", dated Mar. 20, 1979, by R. L. Doucette.
Reference is particularly made to prior art FIG. 1 of the Doucette patent which shows the true output Q taken off one of the emitters of a multi-emitter output transister of the typical EFL type gate and prior art FIG. 2 of the patent which shows the gate modified to change the voltage level of the Q output so that a standard CML gate may be connected thereto. The latter generated a complement output useful for logic systems and described as prior art in the Doucette patent.
In the application of data storage register files (an application different from the applications involved in the Doucette patent), the latch of FIG. 2 of the Doucette patent is typically connected to a separate multiplexer which in turn is connected to a separate decoder for addressing the register. This is shown in FIG. 1 herein where the latch 10 has its Q output connected to a multiplexer 12. This Figure also shows a plurality of latches, 10-10.sup.N, are also connected to the multiplexers 12-12.sup.N and to decoders A and B in a typical prior art system.
Because of the requirement for the separate multiplexers in the prior art which requires a gate for each input Q-Q.sup.N because there is a time delay caused by the interposition of the separate multiplexers between the latches and the separate decoders, and because the separate multiplexers and decoders also require a current source, it is apparent that the elimination of such requirements will improve the speed, performance and power dissipation, and it is to these results that the invention is directed.
It is therefore an object of this invention to provide a new and improved EFL type latch which is merged with a combination decoder-multiplexer circuit to thus improve speed, performance, and reduce power dissipation in CML circuitry.